SysTick Timer registers - Регистры системного таймера

// Configuration of the Cortex-M3 Processor and Core Peripherals 
#define __Vendor_SysTickConfig    0       /* Set to 1 if different SysTick Config is used */


/******  Cortex-M3 Processor Exceptions Numbers ********/
SysTick_IRQn  = -1,   /* 15 Cortex-M3 System Tick Interrupt   */


//-  core_cm3.h
/* Memory mapping of Core Hardware */
#define SCS_BASE         (0xE000E000UL)                   /* System Control Space Base Address */
#define SysTick_BASE     (SCS_BASE +  0x0010UL)           /* SysTick Base Address */
#define SysTick          ((SysTick_Type *)SysTick_BASE)   /* SysTick configuration struct */

typedef struct
{
  __IOM uint32_t CTRL;      /* Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;      /* Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;       /* Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM  uint32_t CALIB;     /* Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;