Регистры DMA (Direct memory access) - прямого доступа к памяти

Имя регистра

Смещение

Наименование

DMA_ISR

0x00

DMA interrupt status register

Регистр статуса прерываний от каналов DMA

DMA_IFCR

0x04

DMA interrupt flag clear register

Регистр сброса флага статуса прерываний от каналов DMA

DMA_CCRx

0x08 + 0x14 * (x-1)

DMA channel x configuration register (x - channel number)

Регистр конфигурации канала x DMA (x - номер канала)

DMA_CNDTRx

0x0C + 0x14 * (x-1)

DMA channel x number of data register (x - channel number)

Регистр количества передаваемых данных по каналу x DMA (x - номер канала)

DMA_CPARx

0x10 + 0x14 * (x-1)

DMA channel x peripheral address register (x - channel number)

Регистр адреса периферии канала x DMA (x - номер канала)

DMA_CMARx

0x14 + 0x14 * (x-1)

DMA channel x memory address register (x - channel number)

Регистр адреса памяти канала x DMA (x - номер канала)


#define PERIPH_BASE           ((uint32_t)0x40000000)     /* Peripheral base address in the alias region */
#define APB1PERIPH_BASE       PERIPH_BASE
#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)


typedef struct
{
  __IO uint32_t ISR;
  __IO uint32_t IFCR;
} DMA_TypeDef;


typedef struct
{
  __IO uint32_t CCR;
  __IO uint32_t CNDTR;
  __IO uint32_t CPAR;
  __IO uint32_t CMAR;
} DMA_Channel_TypeDef;



/******  STM32 specific Interrupt Numbers ***********************************/
...
  DMA1_Channel1_IRQn          = 11,     /* DMA1 Channel 1 global Interrupt  */
  DMA1_Channel2_IRQn          = 12,     /* DMA1 Channel 2 global Interrupt  */
  DMA1_Channel3_IRQn          = 13,     /* DMA1 Channel 3 global Interrupt  */
  DMA1_Channel4_IRQn          = 14,     /* DMA1 Channel 4 global Interrupt  */
  DMA1_Channel5_IRQn          = 15,     /* DMA1 Channel 5 global Interrupt  */
  DMA1_Channel6_IRQn          = 16,     /* DMA1 Channel 6 global Interrupt  */
  DMA1_Channel7_IRQn          = 17,     /* DMA1 Channel 7 global Interrupt  */
...
  DMA2_Channel1_IRQn          = 56,     /* DMA2 Channel 1 global Interrupt  */
  DMA2_Channel2_IRQn          = 57,     /* DMA2 Channel 2 global Interrupt  */
  DMA2_Channel3_IRQn          = 58,     /* DMA2 Channel 3 global Interrupt  */
  DMA2_Channel4_IRQn          = 59,     /* DMA2 Channel 4 global Interrupt  */
  DMA2_Channel5_IRQn          = 60,     /* DMA2 Channel 5 global Interrupt  */
...

В устройствах с контроллером DMA2 есть особенности применения прерываний 4-го и 5-го каналов: DMA2_Channel4_IRQn и DMA2_Channel5_IRQn. Смотреть документацию!