ADC regular sequence register 3 (ADC_SQR3)

Третий регистр назначения регулярных каналов АЦП STM32F10x

Смещение (Address offset): 0x34

Reset value: 0x0000'0000

31	30	29	28	27	26	25	24
Reserved		SQ6[4:0]					SQ5[4]
---		rw					rw
0	0	0	0	0	0	0	0

23	22	21	20	19	18	17	16
SQ5[3:0]				SQ4[4:1]
rw				rw
0	0	0	0	0	0	0	0

15	14	13	12	11	10	9	8
SQ4[0]	SQ3[4:0]					SQ2[4:3]
rw	rw					rw
0	0	0	0	0	0	0	0

7	6	5	4	3	2	1	0
SQ2[2:0]			SQ1[4:0]
rw			rw
0	0	0	0	0	0	0	0

Биты

Имя

Описание

31:30

Reserved

Must be kept at reset value

Зарезервировано. Должно быть сохранено значение после сброса

29:25

SQ6[4:0]

6th conversion in regular sequence

Назначает 6-му каналу в группе регулярных каналов номер входного канала

Номера входных каналов от 0 до 15 (от ADC_IN0 до ADC_IN15) - внешние входы.

ADC1: ADC_IN16 - датчик температуры, ADC_IN17 - опорное напряжение.

ADC2: ADC_IN16, ADC_IN17 - подключены к Vss ("земля").

ADC3: ADC_IN9, ADC_IN14, ADC_IN15, ADC_IN16, ADC_IN17 - подключены к Vss ("земля").

Назначения остальным каналам производятся аналогично.

//- stm32f10x.h

/*******************  Bit definition for ADC_SQR3 register  *******************/

#define  ADC_SQR3_SQ1       ((uint32_t)0x0000001F)     /* SQ1[4:0] bits (1st conversion in regular sequence) */
#define  ADC_SQR3_SQ1_0     ((uint32_t)0x00000001)     /* Bit 0 */
#define  ADC_SQR3_SQ1_1     ((uint32_t)0x00000002)     /* Bit 1 */
#define  ADC_SQR3_SQ1_2     ((uint32_t)0x00000004)     /* Bit 2 */
#define  ADC_SQR3_SQ1_3     ((uint32_t)0x00000008)     /* Bit 3 */
#define  ADC_SQR3_SQ1_4     ((uint32_t)0x00000010)     /* Bit 4 */

#define  ADC_SQR3_SQ2       ((uint32_t)0x000003E0)     /* SQ2[4:0] bits (2nd conversion in regular sequence) */
#define  ADC_SQR3_SQ2_0     ((uint32_t)0x00000020)     /* Bit 0 */
#define  ADC_SQR3_SQ2_1     ((uint32_t)0x00000040)     /* Bit 1 */
#define  ADC_SQR3_SQ2_2     ((uint32_t)0x00000080)     /* Bit 2 */
#define  ADC_SQR3_SQ2_3     ((uint32_t)0x00000100)     /* Bit 3 */
#define  ADC_SQR3_SQ2_4     ((uint32_t)0x00000200)     /* Bit 4 */

#define  ADC_SQR3_SQ3       ((uint32_t)0x00007C00)     /* SQ3[4:0] bits (3rd conversion in regular sequence) */
#define  ADC_SQR3_SQ3_0     ((uint32_t)0x00000400)     /* Bit 0 */
#define  ADC_SQR3_SQ3_1     ((uint32_t)0x00000800)     /* Bit 1 */
#define  ADC_SQR3_SQ3_2     ((uint32_t)0x00001000)     /* Bit 2 */
#define  ADC_SQR3_SQ3_3     ((uint32_t)0x00002000)     /* Bit 3 */
#define  ADC_SQR3_SQ3_4     ((uint32_t)0x00004000)     /* Bit 4 */

#define  ADC_SQR3_SQ4       ((uint32_t)0x000F8000)     /* SQ4[4:0] bits (4th conversion in regular sequence) */
#define  ADC_SQR3_SQ4_0     ((uint32_t)0x00008000)     /* Bit 0 */
#define  ADC_SQR3_SQ4_1     ((uint32_t)0x00010000)     /* Bit 1 */
#define  ADC_SQR3_SQ4_2     ((uint32_t)0x00020000)     /* Bit 2 */
#define  ADC_SQR3_SQ4_3     ((uint32_t)0x00040000)     /* Bit 3 */
#define  ADC_SQR3_SQ4_4     ((uint32_t)0x00080000)     /* Bit 4 */

#define  ADC_SQR3_SQ5       ((uint32_t)0x01F00000)     /* SQ5[4:0] bits (5th conversion in regular sequence) */
#define  ADC_SQR3_SQ5_0     ((uint32_t)0x00100000)     /* Bit 0 */
#define  ADC_SQR3_SQ5_1     ((uint32_t)0x00200000)     /* Bit 1 */
#define  ADC_SQR3_SQ5_2     ((uint32_t)0x00400000)     /* Bit 2 */
#define  ADC_SQR3_SQ5_3     ((uint32_t)0x00800000)     /* Bit 3 */
#define  ADC_SQR3_SQ5_4     ((uint32_t)0x01000000)     /* Bit 4 */

#define  ADC_SQR3_SQ6       ((uint32_t)0x3E000000)     /* SQ6[4:0] bits (6th conversion in regular sequence) */
#define  ADC_SQR3_SQ6_0     ((uint32_t)0x02000000)     /* Bit 0 */
#define  ADC_SQR3_SQ6_1     ((uint32_t)0x04000000)     /* Bit 1 */
#define  ADC_SQR3_SQ6_2     ((uint32_t)0x08000000)     /* Bit 2 */
#define  ADC_SQR3_SQ6_3     ((uint32_t)0x10000000)     /* Bit 3 */
#define  ADC_SQR3_SQ6_4     ((uint32_t)0x20000000)     /* Bit 4 */